CD4000 SERIES PDF

It is still in use today. Wide adoption was initially hindered by the comparatively lower speeds of the designs compared to TTL based designs. Speed limitations were eventually overcome with newer fabrication methods, leaving the older TTL chips to be phased out. The series was extended in the late s and s with new models that were given 45xx and 45xxx designations, but are usually still regarded by engineers as part of the series. In the s, some manufacturers e. The series facilitates simpler circuit design through relatively low power consumption, a wide range of supply voltages , and vastly increased load-driving capability fanout.

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For each IC there is a diagram showing the pin arrangement and brief notes explain the function of the pins where necessary. The notes also explain if the IC's properties differ substantially from the standard characteristics listed below. If you are using another reference please be aware that there is some variation in the terms used to describe input pins.

I have tried to be logically consistent so the term I have used describes the pin's function when high true. For example 'disable clock' on the is often labelled 'clock enable' but this can be confusing because it enables the clock when low false.

An input described as 'active low' is like this, it performs its function when low. Touching a pin while charged with static electricity from your clothes for example may damage the IC! In fact most ICs in regular use are quite tolerant and earthing your hands by touching a metal water pipe or window frame before handling them will be adequate.

It is best to build a circuit using just one logic family, but if necessary the different families may be mixed providing the power supply is suitable for all of them. For example mixing and 74HC requires the power supply to be in the range 3 to 6V. A 74LS output cannot reliably drive a or 74HC input unless a 'pull-up' resistor of 2.

Driving or 74HC inputs from a 74LS output using a pull-up resistor. The has Schmitt trigger inputs to provide good noise immunity. They are ideal for slowly changing or noisy signals. The hysteresis is about 0. This gate has a propagation time which is about 10 times longer than normal so it is not suitable for high speed circuits. The gate output is sufficient to drive four 74LS inputs.

The count advances as the clock input becomes high on the rising-edge. Each output Q0-Q9 goes high in turn as counting advances.

The reset input should be low 0V for normal operation counting When high it resets the count to zero Q0 high. Counting to less than 9 is achieved by connecting the relevant output Q0-Q9 to reset, for example to count 0,1,2,3 connect Q4 to reset. The disable input should be low 0V for normal operation. When high it disables counting so that clock pulses are ignored and the count is kept constant. It can be used to drive the clock input of another to count the tens. The outputs a-g go high to light the appropriate segments of a common-cathode 7-segment display as the count advances.

The maximum output current is about 1mA with a 4. The table below shows the segment sequence in detail. When high it resets the count to zero. The disable clock input should be low 0V for normal operation.

When low it makes outputs a-g low, giving a blank display. The enable out follows this input but with a brief delay. It can be used to drive the clock input of another to provide multi-digit counting.

The is a synchronous counter so its outputs change precisely together on each clock pulse. This is helpful if you need to connect the outputs to logic gates because it avoids the glitches which occur with ripple counters. The count occurs as the clock input becomes high on the rising-edge. Please see below for details of connecting synchronous counters like the in a chain.

These are synchronous counters so their outputs change precisely together on each clock pulse. This is helpful if you need to connect their outputs to logic gates because it avoids the glitches which occur with ripple counters. When reset is high it resets the count to zero , QA-QD low.

The clock input should be low when resetting. Please see below for details of connecting synchronous counters like the and in a chain. The diagram below shows how to link synchronous counters. Notice how all the clock CK inputs are linked. Carry out CO feeds carry in CI of the next counter. Carry in CI of the first counter should be low for , and counters.

Normally a clock signal is connected to the clock input, with the enable input held high. Counting advances as the clock signal becomes high on the rising-edge. For normal operation the reset input should be low, making it high resets the counter to zero , QA-QD low. Counting to less than the maximum 9 or 15 can be achieved by connecting the appropriate output s to the reset input, using an AND gate if necessary.

The diagram below shows how to link and counters. Notice how the normal clock inputs are held low, with the enable inputs being used instead. The complete chain is a ripple counter, although the individual counters are synchronous!

The is a ripple counter so beware that glitches may occur in any logic gate systems connected to its outputs due to the slight delay before the later counter outputs respond to a clock pulse. The count advances as the clock input becomes low on the falling-edge , this is indicated by the bar over the clock label.

This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain. Note that Q2 and Q3 are not available. The reset input should be low for normal operation counting. When high it resets the count to zero all outputs low. Also see these bit counters: and includes internal oscillator. The clock can be driven directly, or connected to the internal oscillator see below.

Note that Q and Q11 are not available. The includes an internal oscillator. The clock signal may be supplied in three ways:.

The appropriate output Q becomes high in response to the BCD binary coded decimal input. The is a BCD binary coded decimal decoder intended for input values 0 to 9 to in binary.

With inputs from 10 to 15 to in binary all outputs are low. The outputs a-g can source up to 25mA. The 7-segment display segments must be connected between the outputs and 0V with a resistor in series with a 5V supply. A common cathode display is required. Display test and blank input are active-low so they should be high for normal operation. When display test is low all the display segments should light showing number 8.

When blank input is low the display is blank all segments off. The store input should be low for normal operation. When store is high the displayed number is stored internally to give a constant display regardless of any changes which may occur to the inputs A-D. The is intended for BCD binary coded decimal. Inputs values from 10 to 15 to in binary will give a blank display all segments off. Supply: 3 to 15V, small fluctuations are tolerated.

Inputs have very high impedance resistance , this is good because it means they will not affect the part of the circuit where they are connected. However, it also means that unconnected inputs can easily pick up electrical noise and rapidly change between high and low states in an unpredictable way. This is likely to make the IC behave erratically and it will significantly increase the supply current.

Outputs can sink and source only about 1mA if you wish to maintain the correct output voltage to drive CMOS inputs. If there is no need to drive any inputs the maximum current is about 5mA with a 6V supply, or 10mA with a 9V supply just enough to light an LED. Fan-out: one output can drive up to 50 inputs. Gate propagation time : typically 30ns for a signal to travel through a gate with a 9V supply, it takes a longer time at lower supply voltages.

It is much greater at high frequencies, a few mW at 1MHz for example. ICs should be left in their protective packaging until you are ready to use them. Note that a series output can drive only one 74LS input. Note the unusual arrangement of the power supply pins for these ICs! The not 2 output is high unless the count is 2 when it goes low. Connecting in a chain Please see below for details of connecting synchronous counters like the in a chain.

Connecting in a chain Please see below for details of connecting synchronous counters like the and in a chain. These contain two separate synchronous counters, one on each side of the IC. The clock signal may be supplied in three ways: From an external source to the clock input, as for a normal counter. RC oscillator as shown in the diagram. R1 should be at least 50k if the supply voltage is less than 7V. R2 should be between 2 and 10 times R1.

Crystal oscillator as shown in the diagram, note that there is no connection to pin 9. Note that the can be used as a 1-of-8 decoder if input D is held low.

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4000 CMOS Series

For each IC there is a diagram showing the pin arrangement and brief notes explain the function of the pins where necessary. The notes also explain if the IC's properties differ substantially from the standard characteristics listed below. If you are using another reference please be aware that there is some variation in the terms used to describe input pins. I have tried to be logically consistent so the term I have used describes the pin's function when high true. For example 'disable clock' on the is often labelled 'clock enable' but this can be confusing because it enables the clock when low false. An input described as 'active low' is like this, it performs its function when low.

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4000 series CMOS Logic ICs

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